Method for reducing single bit data loss in a memory circuit

ABSTRACT

The present invention includes a method for reducing random bit data loss in a memory circuit. The method comprises a semiconductor layer that has a surface. The semiconductor layer is exposed at an elevated temperature to an atmosphere comprising deuterium thereby forming a film on the semiconductor layer comprising deuterium. A memory circuit is fabricated on or within the semiconductor layer.

RELATED APPLICATIONS

This application is a Divisional of U.S. application Ser. No.09/382,442, filed on Aug. 25, 1999, which is incorporated herein byreference.

FIELD OF THE INVENTION

The present invention relates to fabricating electrically programmableand electrically erasable memory cells and particularly, fabricating thecells to substantially eliminate hot-electron degradation effects.

BACKGROUND

Memory circuit arrays positioned on semiconductor chips have become animportant component common to VLSI circuits. Memory circuits rely uponstorage of data in a memory array within a section of a chip designatedfor memory. The memory array is comprised of memory cells.

Memory circuits are of two basic types—volatile memory circuits andnonvolatile memory circuits. A nonvolatile memory circuit does not losestored “bits” or information when the circuit loses power. For avolatile memory circuit, information is lost when the circuit losespower.

ROM or read-only memory is a basic type of nonvolatile memory. Datastored in ROM is a permanent part of the circuit. The ROM circuitprovides precoded information to a user. One variation of ROM is anerasable programmable ROM, commonly referred to as EPROM. To create theerasable feature, a transistor, such as a memory MOS transistor, isselectively charged to impart data to the memory field. The memory fieldis programmed by a procedure of hot electron injection. The memory fieldmay be re-programmed by draining off the charge, removing the chip fromthe circuit and imparting a new memory with an exterior source.

An improvement to EPROM is a memory circuit that can be reprogrammedwhile the chip is in a socket of a machine. This memory circuit, anEEPROM circuit, is prepared for reprogramming by draining charge and bycharging the memory circuit in place. The EEPROM memory circuit isprogrammed and reprogrammed by hot electron injection.

Both EPROM and EEPROM comprise a large number of memory cells havingelectrically isolated gates, referred to as floating gates. Data isstored in the memory cells in the form of charge on the floating gates.Charge is transported to or removed from the floating gates by programand erase operations, respectively.

One other type of memory circuit, a FLASH circuit, is a form of EEPROM,which is a form of electronically erasable, programmable, read onlymemory. FLASH memory is based upon a one-transistor cell design but hasa capacity for in-socket programming and erasure. FLASH memory is a typeof nonvolatile memory. FLASH memory differs from EPROM and EEPROM inthat erase programs are done in blocks.

One prior art memory circuit, illustrated in FIGS. 1(a) and 1(b),comprises a memory 184 with a memory array 198, control logic 194 andaddress logic 196, illustrated in prior art FIG. 1(b). The address logic196 receives an address from an external system, such as amicroprocessor. The control logic 194 receives external commands tostore or to retrieve data to or from the memory array 198 at celllocation(s) provided to the address logic 196 by the external system.Subsequently, the data associated with cell location(s) is respectivelytransmitted to or received from the external system.

The memory 184 may be FLASH memory. The memory array 198 includes aplurality of FLASH cells of each having a floating gate transistor suchas storage transistor 182 of FIG. 1(a). The storage transistor 182comprises two gates, a floating gate stack 170 and a control gate stack172, an active source region 152 a and an active drain region 152 b anda channel 162 also formed in the semiconductor 168. Both the floatinggate stack 170 and the control gate stack 172 are formed by conductors122 and 124 and gate oxides 144 and 146.

Nonvolatile memory storage in a circuit requires a permanent storage ofcharge in the floating gate stack region of the memory circuit.Nonvolatile memory storage in a memory circuit such as an EEPROM or aFLASH memory circuit is made possible by materials used in the gateregion, including materials added by doping and by structural design ofthe gate region. These materials include silicon of a wafer supportingthe circuit and silicon oxide formed during gate fabrication.

FLASH memory is especially sensitive to degradation effects due to asubstantial number of hot electrons generated in each memory cell duringflash memory cycling. Specifically, during an operation of programming amemory cell, a positive programming voltage is applied to the controlgate stack 172. This positive programming voltage attracts electronsfrom the semiconductor 168 which is a p-type substrate and causes themto accumulate at the surface of channel region 162. A voltage on drain152 b is increased and the source 152 a is connected to ground. As thedrain-to-source voltage increases, electrons flow from the source 152 ato drain 152 b via the channel region 162. As electrons travel towarddrain 152 b they acquire substantially large kinetic energy and arereferred to as hot electrons. The hot electrons are injected through theoxide layer 146 and are stored on floating gate stack 170.

FLASH memory cycling occurs when the FLASH memory is repeatedlyprogrammed and erased. With FLASH memory cycling, a significant numberof substrate hot electrons are trapped within an insulating gate oxidelayer 146, such as is shown in the prior art FLASH circuit in FIG. 1(a),that separates a drain region 152 a from the floating gate stack 170.The greater the number of cycles that a FLASH memory device is subjectedto, the greater the number of carriers that become trapped in the gateoxide.

The trapping and accumulation of hot electrons starts a chargingprocess. Gradually, as the charge on the floating gate increases, theelectric field in oxide layer 144 decreases and eventually loses itscapability of attracting any more of the hot electrons to the floatinggate 170. At this point, the floating gate stack 170 is fully charged.The negative charge from the hot electrons collected in the floatinggate stack 170 raises the cell's threshold voltage above a logic 1voltage. If the voltage on control gate stack 172 is brought to a logic1 during a read operation, the cell will barely turn on. Senseamplifiers are used in the memory to detect and amplify the state of thememory cell during a read operation. Thus, data is read from a memorycell based upon its “ON” characteristics.

Hot electron degradation effects have been observed in FLASH memories intwo ways. Most noticeably, the erase/programming times for a givenmemory array are increased far beyond their normal limits. Thisphenomena is frequently referred to a “erasetime/programtime push-out.”This means that as the devices are repeatedly cycled, a greater amountof erase/program time must be allotted for each successive cycle inorder to insure that the entire array is completely charged ordischarged.

A second indication that degradation effects are manifested in a FLASHmemory cell array is an excess charge loss which renders the memorydevices unreliable. That is, even though the device is initiallyprogrammed to an “apparently” correct level, with time that programminglevel may drop below the limits of reliable operation. This “apparent”charge loss of the devices occurs after extensive program-erase cycles.

Several methods have been developed in attempts to reduce hot electroninduced degradation. One method uses a lightly doped drain, LDD,positioned proximal to a highly doped region. The LDD spreads anelectric field in an attempt to prevent the hot electrons from gainingsufficient energy to break the silicon-hydrogen bonds. The use of an LDDreduces but does not eliminate the effects of hot electron induceddegradation. Furthermore, the use of an LDD may further degrade thetransistor by creating higher resistance than desired.

Another method is described in an article by F. C. Hsu et al., “Effectof Final Annealing on Hot-Electron-Induced MOSFET Degradation,” IEEEDevice Letters, vol. ed 1-6, No. 7, July 1985. A metal oxidesemiconductor field effect transistor (MOSFET) as used herein refers toa field-effect transistor containing a metal gate over thermal oxideover silicon. The method described in Hsu et al. for reducing theeffects of hot electron induced degradation has included a use of anitrogen ambient rather than a hydrogen ambient to perform a finalanneal in a post-metallization procedure in order to reduce the amountof hydrogen available to bond with silicon. Although the use of thenitrogen ambient reduced the amount of hydrogen available to bond withsilicon, it was difficult to eliminate hydrogen entirely, since many ofthe procedures employed to fabricate a MOSFET are hydrogen-dependent.Thus, while the use of nitrogen ambient reduced the amount of hydrogenpresent, the use did not eliminate hydrogen nor the problems caused byhot electron induced degradation.

Electrons are removed from the floating gate to erase the memory cell.Many memories, including FLASH memories, use Fowler-Nordheim (FN)tunneling to erase a memory cell. The erase program is accomplished byelectrically floating the drain, grounding the source, and applying ahigh negative voltage to the control gate. This creates an electricfield across the gate oxide and forces electrons off the floating gate.The electrons then tunnel through the gate oxide.

One of the difficulties with FLASH memories has been with the eraseoperation using Fowler-Nordheim tunneling. The erase operation requireshigh voltages, and is relatively slow. Further, an erratic over erasecan be induced as a result of the very high erase voltages used. Thesevery high erase voltages are a fundamental problem arising from the highelectron affinity of bulk silicon or large grain polysilicon particlesused as the floating gate. The high erase voltages create a very hightunneling barrier. Even with high negative voltages applied to the gate,a large tunneling distance is experienced with a very low tunnelingprobability for electrons attempting to leave the floating gate. Thisresults in long erase times because the net flux of electrons leavingthe gate is low. Thus, the tunneling current discharging the gate islow.

Other phenomena result as a consequence of this very high negativevoltage. One phenomenon is hole injection. Hole injection into the oxideis experienced which can result in erratic over erase, damage to thegate oxide itself and the introduction of trapping states.

A reference of K. Hess et al., IEEE Transactions on Electron Devices,vol. 45, No. 2, February 1998, entitled, “Giant Isotope Effect in HotElectron Degradation of Metal Oxide Silicon Devices,” at pp. 406 to 416,describes a giant isotope effect of hot electron degradation. The effectwas observed in integrated circuits of a complementary metal oxidesilicon (CMOS) type. To study this effect, the authors passivatedsilicon wafers with deuterium instead of hydrogen.

The authors observed that the desorption efficiency for deuterium fromsilicon was about a factor of fifty lower than for hydrogen for energiesabove about 5 eV. The authors concluded that hydrogen migration playedsome role in mechanisms responsible for gate oxide wear-out. Inparticular, the authors concluded that a large deuterium content at asilicon wafer interface could be correlated to an improvement intransistor lifetime for some types of transistors. The authorsattributed the longer lifetime to minimized damage occurring during asingle event of hot electron injection.

With hot electron injection, the steady state of hydrogen within asilicon dioxide film is disrupted because the energy from the injectionionizes the hydrogen to H+ ions. It is believed that electrons from thehot electron injection excite or collide with hydrogen that is bound tosilicon or polysilicon at the Si/Si0 ₂ interface. A collection of H+ions drift to a memory storage area of the memory circuit, such as afloating gate, and combine with stored electrons.

The stored electrons are ordered within fields so as to “hold”nonvolatile memory within the circuit. Once hydronium ions are combinedwith electrons, hydrogen gas is formed and data within the memory isdestroyed. As a consequence, the transistor is degraded.

DESCRIPTION OF THE DRAWINGS

FIG. 1(a) is a cross-sectional view of one prior art embodiment of aFLASH device.

FIG. 1(b) is a prior art block diagram of a memory.

FIG. 2 is a cross-sectional view of one embodiment of a FLASH device ofthe present invention.

FIG. 3 is a cross-sectional view of one other embodiment of a FLASHdevice of the present invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention.

For purposes of this specification, the terms “chip”, “wafer” and“substrate” include any structure having an exposed surface ofsemiconductor material with which to form integrated circuit (IC)structures. These terms are also used to refer to semiconductorstructures during processing, and may include other layers that havebeen fabricated thereupon. The terms include doped and undopedsemiconductors, epitaxial semiconductor layers supported by a basesemiconductor or insulator, as well as other semiconductor structureswell known in the art. The term “conductor” is understood to includesemiconductors, and the term “insulator” is defined to include anymaterial that is less electrically conductive than the materialsreferred to as “conductors.” The following detailed description is,therefore, not to be taken in a limiting sense. The term “hydrogenisotope” refers to deuterium, tritium and compounds that includedeuterium and tritium.

A FLASH memory circuit according to one embodiment of the presentinvention, illustrated generally at 200 in FIG. 2 and a memory cell ofthe present invention, illustrated generally at 210 in FIG. 2 arefabricated employing metal- oxide-semiconductor, MOS, technology as wellas non-metal based technology utilizing materials such as polysilicon.One embodiment of a method for fabricating the FLASH memory circuit 200utilizes MOS fabrication techniques in conjunction with a process forfabricating a FLASH memory device, i.e. EPROM, or an array which relieson hot electron injection of carriers between a substrate and a floatinggate member of the memory cell.

One embodiment of the method of the present invention, for reducing lowtemperature single bit data loss in memory such as FLASH memory,comprises providing a silicon wafer with a silicon surface; fabricatinga gate region in the wafer; and treating a portion of the siliconsurface to form a thin layer of insulator film adjacent to the gateregion and under the gate region. The thin layer of insulator film isprepared using an annealing medium that comprises deuterium.

The FLASH memory circuit 200 comprises the FLASH cell 210 that comprisesa floating gate 204 and a control gate 202 as well as an active region212 and a channel 214 formed in a silicon semiconductor 216. Both thefloating gate 204 and control gate 202 are formed by conductors 216 and218 and gate oxide 220 and 222. The gate oxide 220 and 222 is comprisedof silicon oxide or silicon nitride or silicon oxynitride orcombinations of these oxides. A hydrogen isotope such as deuterium,designated “D” in FIG. 2, is entrapped within the film. The FLASH memorycircuit of the present invention is resistant to single bit data losswithin its memory at low temperature.

Repeated cycling of a FLASH memory results in charge loss from thefloating gate 204 and a corresponding degradation in device performance.It is believed that this phenomena is caused in part by the introductionof hydrogen into the active regions of the field effect device. Thepresence of hydrogen enhances interface state generation and causesdevice degradation. It is also believed, that a single bit data losstype of degradation is reduced by annealing silicon regions proximal tothe memory circuit in a medium enriched in deuterium, and forming thegate oxide 220 and 222 which is enriched in deuterium. The annealing isperformed, in one embodiment, as a final post-metallization anneal. Theanneal is performed in an atmosphere comprising approximately fourpercent to one-hundred percent deuterium with the remaining gas being aninert gas or nonreactive gas such as nitrogen or a combination of theinert gas and the nonreactive gas.

Intermediate anneals performed during memory circuit fabrication mayalso be performed in a deuterium atmosphere or other Hydrogen isotopeatmosphere. These intermediate anneals include oxidation of specificmemory cell layers in an atmosphere that comprises either deuterium or acompound that includes deuterium such as D₂ O, D₂, or ND₃.

One other embodiment of the memory cell device of the present inventionis illustrated at 300 in FIG. 3. The FLASH memory cell 300 is alsofabricated utilizing metal-oxide-semiconductor, MOS, techniques. TheFLASH memory cell 300 is fabricated on a p-type silicon substrate 330.Field oxide isolation regions 350 are defined using a silicon nitridemasking layer. The field oxide regions 350 are then grown, in oneembodiment, to a thickness of about 7500 Angstroms.

Following formation of the field oxide regions 350, a high-gradetunneling oxide 340 is thermally grown above a channel region 420 of thesubstrate. After that, in one embodiment, a phosphorous-dopedpolycrystalline silicon, polysilicon, layer 360 is deposited and etchedin a pattern which will subsequently form the floating gates for each ofthe memory cells. After a thermally grown dielectric layer 320 is grownover layer 360, a second layer of polysilicon 370 is deposited andetched in a pattern which runs generally perpendicular to the pattern oflayer 360. The second layer 370 defines the control gate for the memorydevice. Layer 360 forms the floating gate of the device. Control gatemember 370 stretches over the active channel region 420 of the cell andextends beyond the tunneling region to the next cell, thereby forming aword line in an array.

The source and drain regions for the cells are formed after thepolysilicon, poly 2 layer 370 has been defined. In one embodiment, anarsenic implant is used to form a source drain region. The source drainregion may receive an additional phosphorous implant, thereby forming adeeper phosphorous source junction because the phosphorous diffuses intothe silicon. The phosphorous implant causes the source side to have adeeper and more gradual dopant concentration gradient than the drainside. The deeper implantation reduces substrate current duringelectrical erase. The source drain region may also be formed by ordinarydiffusion steps. Region 310 represents a common source within the FLASHmemory array.

After the source and drain regions are formed, a thermal oxide layer 230is grown over the source/drain and polysilicon gate surfaces. A CVDdielectric film 380 is then deposited on top of the thermal oxide toplanarize the device.

To open the drain contact, the device is masked and etched until an areaof silicon directly over the drain region is exposed. This becomes thedrain contact region 340. In one embodiment, an aluminum metallizationlayer 400 is deposited over the device to connect the drain regions andforms the bit lines of the memory array.

The entire device is then passivated by annealing an insulating layer410 in an atmosphere that comprises deuterium and a nitrogen ambient sothat the layer 410 is comprised of oxynitride and deuterium. Theinsulating layer 410 may also be comprised of silicon oxide anddeuterium. It is believed that forming a passivation layer thatcomprises deuterium retards diffusion of hydrogen atoms under themetallization layer and migration to the channel region 420. Thehydrogen atoms cannot then interact with continuous charge transfer thatoccurs in the gate oxide region of the memory devices.

Passivation as used herein refers to a process whereby a film is grownon a surface to either chemically protect it from the environment or toprovide electronic stabilization of the surface. The method of thepresent invention includes embodiments wherein intermediate passivationin an atmosphere comprising deuterium is performed on layers such as 220and 222 in FIG. 2. The method of the present invention also includesembodiments wherein a device passivation in an atmosphere comprisingdeuterium or other Hydrogen isotope is performed on a layer such as 410in FIG. 3.

One conventional silicon passivation reaction, free from deuterium isthe following:

Si (solid)+H₂ O (gas)----------->SiO₂ (solid)+2H₂(gas). With theconventional silicon passivation reaction of an intermediate layer,hydrogen remaining in the oxide proximal to a gate is believed to be ina steady state relationship with the oxide. Substituting deuterium ionsor other Hydrogen isotopes for protons in the process of surface siliconoxide formation in and proximal to memory storage areas such as gateregions is believed to produce a reduction in the drift of positivelycharged particles. In one other passivation embodiment, passivation of asilicon/silicon dioxide interface of a wafer comprises a treatment of adangling bond with H₂ in order to make a passivated dangling bond andhydrogen gas.

The passivation reaction using deuterium or other Hydrogen isotope inorder to form silicon dioxide, is as follows:

Si (solid)+D₂O (gas)-------->SiO₂ (solid)+2 D₂ (gas).

Passivation utilizing one embodiment of the method of the presentinvention is performed in a deuterium or other Hydrogen isotopeatmosphere at a temperature of 400° C. to 450° C. for 0.5 to 2 hours.The percentage of deuterium in the passivating gas is at least about 10percent by volume and may be about 100 percent. Other non-reactivecomponents of the passivation gas include helium or nitrogen gas. Thepassivation occurs as a consequence of annealing the silicon/silicondioxide surface of the semiconductor wafer. In addition to this thermaloxidation-based method, deuterium may be introduced into a silicondioxide layer by pyrolytic diffusion from the gas or from a plasma or RFsputter deposition.

Hydrogen is replaced by deuterium in a silicon nitride film by exposinga silicon substrate to ammonia in an atmosphere enriched in deuterium ata temperature range of 950° C. to 1200° C. In one embodiment, theammonia is present as a component in a gaseous mixture of deuterium with30 percent by volume ammonia.

Silicon oxynitride films, SiOxNy, are formed by nitridation of siliconoxide films. These films may be made with D₂, D₂O and ND₃ in order toreplace hydrogen in the films with deuterium. This film array is made byutilizing the reactants D₂, D₂O and ND₃ in sequential reactions. Thesequential reactions are for the preparation of silicon dioxide andsilicon nitride layers of the film sandwich. Deuterium may also beintroduced in or proximal to the gate region by targeted deuteriumtreatment, such as ion implantation, in a particular oxide and byannealing the entire device in a deuterium atmosphere.

It is to be appreciated that the method and memory circuit of thepresent invention have been described in particular detail with respectto preferred processes and structures. The present invention, however,is not intended to be limited to these preferred embodiments. Oneskilled in the art will readily recognize that the actual method andcircuit may be adjusted to accommodate particular conditions.

1. A tunneling oxide component of a non-volatile, electrically alterable semiconductor FLASH memory circuit having a programming operation and an erase operation and a gate, the tunneling oxide component comprising Hydrogen isotope wherein the tunneling oxide component is at least partially adjacent the gate region, wherein single bit data loss is prevented in both the programming operation and the erase operation of the FLASH memory circuit.
 2. The tunneling oxide component of claim 1, comprising a silicon dioxide film comprising Hydrogen isotope.
 3. The tunneling oxide component of claim 1, comprising a silicon nitride film comprising Hydrogen isotope.
 4. The tunneling oxide component of claim 1, comprising a film comprising silicon dioxide, silicon nitride, and Hydrogen isotope.
 5. The tunneling oxide component of claim 1, comprising a film comprising silicon oxynitride.
 6. The tunneling oxide component of claim 1, comprising a film annealed in an atmosphere comprising water vapor.
 7. The tunneling oxide component of claim 1, comprising a film annealed in an inert gas.
 8. The tunneling oxide component of claim 1, comprising a film annealed in an atmosphere comprising nitrogen.
 9. The tunneling oxide component of claim 1, comprising a film annealed in an atmosphere comprising a compound comprising nitrogen.
 10. A thermal oxide component of a non-volatile, electrically alterable semiconductor FLASH memory circuit having a programming operation and an erase operation and a gate, the tunneling oxide component, comprising Hydrogen isotope wherein the tunneling oxide component is at least partially adjacent the gate region, wherein single bit data loss is prevented in both the programming operation and the erase operation of the FLASH memory circuit.
 11. The thermal oxide component of claim 10, comprising a silicon dioxide film comprising Hydrogen isotope.
 12. The thermal oxide component of claim 10, comprising a silicon nitride film comprising Hydrogen isotope.
 13. The thermal oxide component of claim 10, comprising a film comprising silicon dioxide, silicon nitride, and Hydrogen isotope.
 14. The thermal oxide component of claim 10, comprising a film comprising silicon oxynitride.
 15. The thermal oxide component of claim 10, comprising a film annealed in an atmosphere comprising water vapor.
 16. The thermal oxide component of claim 10, comprising a film annealed in an inert gas.
 17. The thermal oxide component of claim 10, comprising a film annealed in an atmosphere comprising nitrogen.
 18. The thermal oxide component of claim 10, comprising a film annealed in an atmosphere comprising a compound comprising nitrogen. 